A known integrated gate commutated thyristor (IGCT) structure is shown in FIG. 1. The IGCT (which may hereinafter be referred to as a “device”) 100 includes a cathode side 11 and an anode side 12, which is arranged opposite to the cathode side 11. It is constructed as a four-layer p-n-p-n structure with layers of different conductivity types. The four-layer structure defines an inner structure of a thyristor, which can be turned-off via a gate electrode 4. The layers are arranged between a cathode electrode 2 on the cathode side 11 and an anode electrode 3 on the anode side 12 in the following order: (i) an n doped cathode layer 5 with a central area, which is surrounded by a lateral edge, which cathode layer 5 is in direct electrical contact with the cathode electrode 2; (ii) a p doped base layer 6; (iii) an (n−) doped drift layer 7, wherein the drift layer 7 has a lower doping concentration than the cathode layer 5; (iv) an n doped buffer layer 9, which has a higher doping concentration than the drift layer 7; and (v) a p doped anode layer 8, which is in electrical contact with the anode electrode 3.
The gate electrode 4 is arranged on the cathode side 11 lateral to the cathode electrode 2, and the gate electrode 4 is in electrical contact with the base layer 6, but electrically separated from the cathode electrode 2. The p doped base layer 6 includes a first layer 61 as a continuous layer over the whole plane of the device and a second layer 63, which is arranged between the first layer 61 and the drift layer 7. The second layer 63 is also a continuous layer over the whole plane of the device, and the second layer 63 has a lower doping concentration than the first layer 61.
During turn-off, the device gate voltage is negatively biased and most holes are attracted towards the gate electrode 4. During high stress such as high voltage and high current turn-off switching, the device enters dynamic avalanche whereas the peak electric field is distributed uniformly in the active region along the whole main blocking junction between the cathode layer 5 and the base layer 6. The avalanche-generated holes follow the path towards the gate terminal including the regions directly positioned below the (n++) cathode layer 5 as shown in FIG. 2. The width of the cathode layer 5 is generally above 100 μm depending on the design. Therefore, many holes flow a substantial distance directly in the (p+) doped first layer 61 along the junction between the (n++) cathode layer 5 and the (p+) first layer 61. In the region where strong curvature occurs in the n++/p+ junction, a high concentration of holes could result in relatching of the device and hence, failure.
Different documents deal with another semiconductor type, GTOs, which have highly p doped layers, but for different purposes.
U.S. Pat. No. 4,843,449 discloses a GTO which includes a p doped base layer and above it, an (n+)-doped emitter layer. The (n+) emitter layer is created by either local diffusion of n-particles or by initially creating a homogeneous (n+)-layer, which is then selectively etched away. In order to from a different layer resistance a more strongly doped p layer can be made after the etching in the areas, in which the p-base layer emerges on the surface. The (p+) doped layer touches, but does not cover the edge of the emitter layer.
U.S. Pat. No. 5,387,806 discloses a GTO with a p-base layer and a more highly doped (p+) layer. The (p+) layer is arranged between gate electrode and p base layer, and is terminated laterally to the gate electrode such that the base layer is arranged between and thereby separates the (p+) layer from the cathode layer. There is no (p+) layer arranged between cathode layer and the p base layer, and the (p+) layer does not cover the lateral edge of the cathode layer.
JP 57 201078 discloses a GTO with a p+ layer between gate electrode and p base layer. The p+ layer is not in contact with the (n+) emitter layer.